Application and CAD for Reconfigurable Accelerators and Adaptive Systems

Computer architectures, CAD flows, and adaptive acceleration frameworks for programmable and reconfigurable systems

Overview

Application and CAD for Reconfigurable Accelerators and Adaptive Systems is an RCSL research track led by Dr. Shreejith Shanker. The track focuses on computer architectures, CAD flows, and distributed acceleration frameworks that improve compute efficiency, network performance, and runtime adaptability through close hardware-software interaction.

Fully programmable and reconfigurable platforms are a key enabler in this work, allowing both applications and their underlying hardware to be adapted at design time or runtime. Our goal is to connect application requirements, compiler and CAD methods, and accelerator architecture design so that future programmable systems can be more efficient, adaptive, and easier to deploy across technology domains.

Research Themes

  • Reconfigurable computer architectures and accelerator fabrics
  • CAD flows, compilation, and mapping strategies for programmable hardware
  • Hardware-software co-design for application-specific accelerators
  • Design space exploration and optimisation for performance, energy, and resource efficiency
  • Lightweight and quantised deep learning for embedded and edge platforms
  • Distributed and network-coupled acceleration frameworks
  • Runtime adaptability for dynamic, resource-constrained, and safety-critical systems

Application Domains

  • Lightweight deep learning and AI inference on embedded platforms
  • Media, image, and video processing accelerators
  • Communication and network-oriented computing systems
  • Autonomous and safety-critical embedded platforms
  • Smart energy, EV charging, and grid-aware optimisation infrastructure
  • Distributed sensing and collaborative optimisation systems

Representative Projects

  • EMERALD: sustainable media workflows with energy-aware profiling and accelerator integration for post-production pipelines
  • HARMONIC-AI: ultra-lightweight AI and optimisation for harmonic management in EV charging and grid-tied energy systems
  • Light-weight AI acceleration: quantised deep-learning acceleration for line-rate intrusion detection in in-vehicle networks
  • Speculation in FPGA CAD: speculative optimisation techniques for improving FPGA CAD flows
  • Quantised LSTMs: compilation and backend support for quantised recurrent models on FPGA platforms
  • DISCLOSE: distributed optimisation frameworks for privacy-preserving smart energy management

Lead Investigator

Dr. Shreejith Shanker is an Assistant Professor in the Department of Electronic & Electrical Engineering at Trinity College Dublin and serves as the Principal Investigator of RCSL. He leads this research area within the lab, with work spanning reconfigurable architectures, distributed accelerators, and adaptive computing systems for communication, media, autonomous, and smart energy applications.