Research

RCSL works across two complementary layers of computing systems research.

Application and CAD for Reconfigurable Accelerators and Adaptive Systems

Led by Dr. Shreejith Shanker, this research area focuses on computer architectures, CAD flows, and distributed acceleration frameworks that improve compute efficiency, network performance, and runtime adaptability through close hardware-software interaction. Fully programmable and reconfigurable platforms are a key enabler, allowing both applications and their underlying hardware to be adapted at design time or runtime.

Current work explores sustainable, adaptable, and energy-efficient accelerators for lightweight deep learning, media and video processing, communication networks, autonomous systems, and smart energy infrastructure. We investigate integration approaches, algorithmic and compiler optimisations, and design space exploration schemes for co-designing applications with their accelerators.

VLSI for Custom Chips

Led by Dr. George Floros, the VLSI for Custom Chips research area focuses on EDA, VLSI design techniques, semiconductor device modelling, circuit simulation, IC thermal analysis, and long-term reliability for modern custom and programmable chips. The area connects device-aware modelling and circuit-level analysis with machine learning methods for optimising future VLSI systems.