Reconfigurable Computing Systems Lab
Aras An Phiarsaigh
Trinity College Dublin
RCSL brings together researchers working across the hardware-software stack for next-generation computing systems. The lab operates at two complementary levels: application and CAD methods for reconfigurable accelerators and adaptive systems, led by Dr. Shreejith Shanker, and VLSI for Custom Chips, led by Dr. George Floros.
Across these areas, our vision is to explore the interplay between hardware and software, and between computation and communication, to reimagine digital systems and infrastructure across technology domains. Our research spans lightweight embedded systems, in-vehicle safety-critical architectures, distributed and network-coupled accelerators, energy-efficient deep neural network acceleration, high-quality image and video processing accelerators, and the VLSI design techniques needed for reliable next-generation programmable chips.
news
| Jun 30, 2026 | Paper Updates! |
|---|---|
| May 02, 2026 | New PD joins the team! |
| Jun 01, 2025 | Congrats, Dr. Khandelwal! |
| May 01, 2025 | First paper! |
| Apr 09, 2025 | First paper! |
selected publications
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- Extensible FlexRay Communication Controller for FPGA-Based Automotive SystemsTransactions on Vehicular Technology, 2015
- Virtualized FPGA accelerators for efficient cloud computingIn 2015 IEEE 7th International Conference on Cloud Computing Technology and Science (CloudCom), 2015
- VEGa: A high performance vehicular Ethernet gateway on hybrid FPGAIEEE Transactions on Computers, 2017
- Efficient spectrum sensing for aeronautical LDACS using low-power correlatorsIEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2018
- Build automation and runtime abstraction for partial reconfiguration on Xilinx Zynq Ultrascale+In 2020 International Conference on Field-Programmable Technology (ICFPT), 2020
- Real-time zero-day Intrusion Detection System for Automotive Controller Area Network on FPGAsIn 34th IEEE International Conference on Application-specific Systems, Architectures and Processors, 2023
- Exploring Highly Quantised Neural Networks for Intrusion Detection in Automotive CANIn 33rd International Conference on Field-Programmable Logic and Applications, 2023
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- SecCAN: An Extended CAN Controller with Embedded Intrusion DetectionIEEE Embedded Systems Letters, 2025
- FAV-NSS: An HIL Framework for Accelerating Validation of Automotive Network Security StrategiesIn International Conference on Application-specific Systems, Architectures and Processors (ASAP), 2025
- FINN-GL: Generalized Mixed-Precision Extensions for FPGA-Accelerated LSTMsIn International Conference on Field-Programmable Logic and Applications, 2025
- Simopt-Power: Leveraging Simulation Metadata for Low-Power Design SynthesisIn IEEE Nordic Circuits and Systems Conference (NorCAS), 2025
- An Empirical Study of Reducing AV1 Decoder Complexity and Energy Consumption via Encoder Parameter TuningIn IEEE Picture Coding Symposium (PCS), 2025
- ReTiDe: Real-time Denoising for Energy Efficient Motion Picture Processing with FPGAsIn ACM SIGGRAPH European Conference on Visual Media Production (CVMP), 2025
- LogicSparse: Enabling Engine-Free Unstructured Sparsity for Quantised Deep-learning AcceleratorsIn International Conference on Field-Programmable Technology (ICFPT), 2025
- Workload-Aware Early-Stage Power Delivery Network Optimization via Architectural Power TracesIn International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD) (to appear), 2026
- Context-aware Simopt-Power: Using structural data with simulation metadata to optimise FPGA designsIn International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD) (to appear), 2026