Reconfigurable Computing Systems Lab

RCSL.png

Aras An Phiarsaigh

Trinity College Dublin

RCSL brings together researchers working across the hardware-software stack for next-generation computing systems. The lab operates at two complementary levels: application and CAD methods for reconfigurable accelerators and adaptive systems, led by Dr. Shreejith Shanker, and VLSI for Custom Chips, led by Dr. George Floros.

Across these areas, our vision is to explore the interplay between hardware and software, and between computation and communication, to reimagine digital systems and infrastructure across technology domains. Our research spans lightweight embedded systems, in-vehicle safety-critical architectures, distributed and network-coupled accelerators, energy-efficient deep neural network acceleration, high-quality image and video processing accelerators, and the VLSI design techniques needed for reliable next-generation programmable chips.

news

Jun 30, 2026 Paper Updates!
May 02, 2026 New PD joins the team!
Jun 01, 2025 Congrats, Dr. Khandelwal!
May 01, 2025 First paper!
Apr 09, 2025 First paper!

selected publications

  1. Reconfigurable Computing in Next Generation Automotive Networks
    Shanker Shreejith, Suhaib A Fahmy, and Martin Lukasiewycz
    Embedded Systems Letters, 2013
  2. Extensible FlexRay Communication Controller for FPGA-Based Automotive Systems
    S Shreejith, and S. A Fahmy
    Transactions on Vehicular Technology, 2015
  3. Virtualized FPGA accelerators for efficient cloud computing
    Suhaib A Fahmy, Kizheppatt Vipin, and Shanker Shreejith
    In 2015 IEEE 7th International Conference on Cloud Computing Technology and Science (CloudCom), 2015
  4. VEGa: A high performance vehicular Ethernet gateway on hybrid FPGA
    Shanker Shreejith, Philipp Mundhenk, Andreas Ettner, and 4 more authors
    IEEE Transactions on Computers, 2017
  5. Efficient spectrum sensing for aeronautical LDACS using low-power correlators
    Shanker Shreejith, Libin K Mathew, Vinod A Prasad, and 1 more author
    IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2018
  6. Build automation and runtime abstraction for partial reconfiguration on Xilinx Zynq Ultrascale+
    Alex R Bucknall, Shanker Shreejith, and Suhaib A Fahmy
    In 2020 International Conference on Field-Programmable Technology (ICFPT), 2020
  7. Real-time zero-day Intrusion Detection System for Automotive Controller Area Network on FPGAs
    Shashwat Khandelwal, and Shanker Shreejith
    In 34th IEEE International Conference on Application-specific Systems, Architectures and Processors, 2023
  8. Exploring Highly Quantised Neural Networks for Intrusion Detection in Automotive CAN
    Shashwat Khandelwal, and Shanker Shreejith
    In 33rd International Conference on Field-Programmable Logic and Applications, 2023
  9. Smart network interfaces for advanced automotive applications
    Shanker Shreejith, and Suhaib A Fahmy
    IEEE Micro, 2018
  10. A case for FPGA-based accelerators for energy-efficient motion picture video processing
    Jason Boyle, and Shreejith Shanker
    In Applications of Digital Image Processing XLVI, 2023
  11. SecCAN: An Extended CAN Controller with Embedded Intrusion Detection
    Shashwat Khandelwal, and Shreejith Shanker
    IEEE Embedded Systems Letters, 2025
  12. FAV-NSS: An HIL Framework for Accelerating Validation of Automotive Network Security Strategies
    Changhong Li, Shashwat Khandelwal, and Shanker Shreejith
    In International Conference on Application-specific Systems, Architectures and Processors (ASAP), 2025
  13. FINN-GL: Generalized Mixed-Precision Extensions for FPGA-Accelerated LSTMs
    Shashwat Khandelwal, Jakoba Petri-Koenig, Thomas B Preu\sser, and 2 more authors
    In International Conference on Field-Programmable Logic and Applications, 2025
  14. Simopt-Power: Leveraging Simulation Metadata for Low-Power Design Synthesis
    Eashan Wadhwa, and Shanker Shreejith
    In IEEE Nordic Circuits and Systems Conference (NorCAS), 2025
  15. An Empirical Study of Reducing AV1 Decoder Complexity and Energy Consumption via Encoder Parameter Tuning
    Vibhooti Vibhooti, Julien Zouein, Shreejith Shanker, and 2 more authors
    In IEEE Picture Coding Symposium (PCS), 2025
  16. ReTiDe: Real-time Denoising for Energy Efficient Motion Picture Processing with FPGAs
    Changhong Li, Rosa Cunningham Fernandez, Clemont Bled, and 1 more author
    In ACM SIGGRAPH European Conference on Visual Media Production (CVMP), 2025
  17. LogicSparse: Enabling Engine-Free Unstructured Sparsity for Quantised Deep-learning Accelerators
    Changhong Li, Biswajit Basu, and Shanker Shreejith
    In International Conference on Field-Programmable Technology (ICFPT), 2025
  18. Workload-Aware Early-Stage Power Delivery Network Optimization via Architectural Power Traces
    Oran Hayes, Maria Pantazi-Kypraiou, Athanasios Tziouvaras, and 4 more authors
    In International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD) (to appear), 2026
  19. Context-aware Simopt-Power: Using structural data with simulation metadata to optimise FPGA designs
    Eashan Wadhwa, George Floros, and Shanker Shreejith
    In International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD) (to appear), 2026